1. Field of the Invention
The present invention relates to a switching power supply apparatus.
2. Related Art
A conventional switching power supply is described below with reference to the diagrams. FIG. 8 is a circuit diagram showing an outline of a conventional insulating-type switching power supply apparatus in which the input side and the output side are electrically insulated.
The switching power supply apparatus is configured such that AC electric power applied to a main input terminal 101 from a commercial power supply or the like, for example, is rectified by a rectifier 102 comprising a diode bridge or the like, smoothed by an input capacitor 103, and applied as DC voltage Vin to a first primary winding 104a of a transformer 104 for electric power conversion, as shown in FIG. 8. This primary winding 104a is connected to a switching element 105 comprising an N-type power MOSFET or the like, for example, and the switching power supply apparatus generates an electromotive force by way of magnetic induction in a secondary winding 104c of the transformer 104 by causing the switching element 105 to perform switching action. The switching power supply apparatus then rectifies and smoothes, by means of an output capacitor 108 and a diode 107 connected to the secondary winding 104c, the AC electric power from the electromotive force that is produced in the secondary winding 104c, and supplies the power to a load 110 connected to a main output terminal 109 as the DC power of output voltage Vo.
The dotted line 120 in FIG. 8 represents a semiconductor device. The semiconductor device comprises the switching element 105 and a control circuit 106 for controlling the switching action of the switching element 105; and has three terminals, namely, a drain terminal TD and a source terminal TS for the switching element 105, and a control terminal TC for the control circuit 106.
A second primary winding (hereinafter referred to as auxiliary winding) 104b is provided to the transformer 104. Electromotive force is produced in the auxiliary winding 104b by way of magnetic induction through the switching action of the switching element 105, in the same manner as the secondary winding 104c. 
The auxiliary power supply circuit 111 comprising a diode 112 and an output capacitor 113 rectifies and smoothes the AC electric power from the electromotive force that is generated in the auxiliary winding 104b, and outputs this power as an auxiliary power supply voltage Vcc.
This auxiliary power supply voltage Vcc is input to the control terminal TC. The control circuit 106 uses this auxiliary power supply voltage Vcc as a drive signal, and also uses this voltage as a feedback signal for stabilizing the output voltage Vo because the auxiliary power supply voltage Vcc and the output voltage Vo are proportional to the winding ratio of the auxiliary winding 104b and the secondary winding 104c. In other words, the control circuit 106 controls the switching action of the switching element 105 on the basis of the auxiliary power supply voltage Vcc so that the output voltage Vo remains stable at a prescribed voltage.
The control circuit 106 is described below.
An oscillator 121 first generates a switching signal for inducing a switching action (a repeating ON/OFF action) in the switching element 105. In other words, the oscillator 121 generates and outputs a signal CLK for determining the switching frequency of the switching element 105, and a maximum duty cycle signal MDC for determining the maximum duty cycle of the switching element 105.
An error amplifier 122 further generates and outputs an error voltage signal VEAO that is the voltage value that corresponds to the difference between the auxiliary power supply voltage Vcc and the reference voltage. More specifically, when the auxiliary power supply voltage Vcc that is input to the control terminal TC and resistively divided falls below the prescribed reference voltage that is set in advance, the error amplifier 122 generates and outputs the error voltage signal VEAO comprising this difference to an element current detecting comparator 124. The voltage of the error voltage signal VEAO decreases as the auxiliary power supply voltage Vcc increases, and increases as the auxiliary power supply voltage Vcc decreases.
The element current detecting circuit 123 detects the element current ID that flows from the primary winding 104a of the transformer 104 to the switching element 105, converts the result into a voltage signal that corresponds to the current value thereof, and outputs the result to the element current detecting comparator 124 as an element current detecting signal VCL.
The element current detecting comparator 124 compares the voltage of the element current detecting signal VCL and the error voltage signal VEAO; and the amount of current that flows into the switching element 105 is adjusted and the output voltage Vo stabilized at a prescribed voltage by generating and outputting a comparison signal for turning off the switching element 105 on the basis of this comparison result. More specifically, the element current detecting signal 124 outputs a HIGH signal (The electric potential is a high-level signal, and the same applies hereinafter.) to the one of the input terminals of the AND circuit 130 when the switching element 105 is turned on, and the voltage of the element current detecting signal VCL increases and becomes equivalent to the voltage of the error voltage signal VEAO. The switching element 105 is turned off when this HIGH signal is input to the RESET terminal of an RS flip-flop circuit 126 that is described below.
The switching signal control circuit 125 comprises the RS flip-flop circuit 126, a NAND circuit 127, and a gate driver 128. The RS flip-flop circuit 126 receives a clock signal CLK that is output from the oscillator 121 to the SET terminal, and receives a signal that is output from the AND circuit 130 to the RESET terminal. The NAND circuit 127 receives a maximum duty cycle signal MDC that is output from the oscillator 121 to one of the input terminals, and receives a signal that is output from the RS flip-flop circuit 126 to the other input terminal. The gate driver 128 receives a signal that is output from the NAND circuit 127, inverts and amplifies this, and outputs a control signal to the switching element 105.
The switching element control circuit 125 controls the ON interval of the switching element 105 by controlling the switching signal on the basis of the comparison signal (the output signal from the AND circuit 130) from the element current detecting comparator 124. In other words, the switching signal control circuit 125 controls the switching signal so that the switching element 105 is turned off when the voltage of the error voltage signal VEAO and the voltage of the element current detecting signal VCL are equal and the comparison signal from the element current detecting comparator 124 is a HIGH signal.
Thus, the control circuit 106, with the auxiliary power supply voltage Vcc that is proportional to the output voltage Vo supplied to the load 110 serving as the feedback signal, controls the element current ID that flows from the primary winding 104a of the transformer 104 to the switching element 105 by controlling the ON interval (the OFF interval) of the switching element 105, and ensures that the output voltage Vo remains stable at a prescribed voltage.
An excess current protecting circuit 129 clamps the maximum voltage value of the error voltage signal VEAO that is output from the error amplifier 122, and prevents excess current from flowing to the switching element 105.
An on-blanking pulse generating circuit 131 that is connected to the other terminal of the AND circuit 130 is subsequently described.
The on-blanking pulse generating circuit 131 outputs a blanking pulse signal that disables the comparison signal from the element current detecting comparator 124 for a fixed interval of time (hereinafter referred to as the “blanking interval”) after the switching circuit 105 has been turned on. The on-blanking pulse generating circuit 131 ensures with the aid of this blanking pulse signal that the switching element 105 is not turned off by a capacitive spike current. More specifically, the on-blanking pulse generating circuit 131 outputs to the AND circuit 130 a blanking pulse signal that is a LOW (a signal that has a low electric potential; same below) signal during the blanking interval, and a HIGH signal after the blanking interval has elapsed.
Thus, the on-blanking pulse generating circuit 131 prevents the oscillation of the switching element 105 from being halted by a capacitive spike current. In other words, because a capacitive spike current is generated and the electric potential of the element current detecting signal VCL that is output from the element current detecting circuit 123 increases sharply when the switching element 105 is turned on, the electric potential of the element current detecting signal VCL and the error voltage signal VEAO become equivalent immediately after turn on, and the element current detecting comparator 124 outputs a HIGH signal. As a result, were the control circuit 106 to be configured so that the comparison signal from the element current detecting comparator 124 is directly input to the RESET terminal of the RS flip-flop circuit 126, the switching element 105 would be turned off immediately after being turned on, and the oscillation of the switching element 105 would be halted. In view of the above, with this switching power supply apparatus, the comparison signal from the element current detecting comparator 124 is prevented from being input to the RESET terminal of the RS flip-flop circuit 126 by the AND circuit 130 and the on-blanking pulse generating circuit 131 while the capacitive spike current is being produced.
The constitution of the on-blanking pulse generating circuit 131 is described below.
A blanking interval generating capacitor 140 is connected between the ground of the control circuit 106 and the input terminal of an inverter 141, as shown in FIG. 8. The inverter 141 outputs a blanking pulse signal that is a LOW signal while the electric potential of the blanking interval generating capacitor 140 is higher than a threshold value voltage, and a HIGH signal when the threshold value voltage is reached.
A P-type transistor 142 and an N-type transistor 143 form an inverting circuit wherein the drain terminals are connected together, a control signal from the gate driver 128 is input to the gate terminals, and the opening and closing thereof are inverted in accordance with this control signal. In other words, when a control signal (HIGH signal) for turning on the switching element 105 is received from the gate driver 128, the P-type transistor 142 is turned off and the N-type transistor 143 is turned on. Conversely, when a control signal (LOW signal) for turning off the switching element 105 is received from the gate driver 128, the P-type transistor 142 is turned on and the N-type transistor 143 is turned off.
The blanking interval generating capacitor 140 is connected to the connecting portion (between the drain terminals) of the P-type transistor 142 and an N-type transistor 143.
A mirror circuit 145 comprises N-type transistors 146 and 147. A constant current source 144 is a constant current source for lowering the electric potential of the blanking interval generating capacitor 140. The constant current source 144 is connected to the N-type transistor 146, and the source terminal N-type transistor 143 is connected to the N-type transistor 147.
The operation of the on-blanking pulse generating circuit 131 is described below.
When the switching element 105 is turned on, a HIGH signal is output from the gate driver 128, the P-type transistor 142 is turned off, and the N-type transistor 143 is turned on. As a result, current that is proportional to the current that flows in the constant current source 144 flows to the N-type transistor 147 by way of the blanking interval generating capacitor 140 due to the mirror effect, and the electric potential of the blanking interval generating capacitor 140 decreases. A HIGH signal is output from the inverter 141 when the electric potential of the blanking interval generating capacitor 140 reaches the threshold value voltage of the inverter 141.
After this switching element 105 is turned on (after a HIGH signal is output from the gate driver 128), the interval of time until the electric potential of the blanking interval generating capacitor 140 reaches the threshold value voltage of the inverter 141 is the blanking interval, and the inverter 141 outputs a LOW signal during this time. The blanking interval is a fixed interval that is determined by the capacitance of the blanking interval generating capacitor 140, the threshold value set by the inverter 141, and the current value of the constant current source 144.
When the switching element 105 is thereafter turned off (when a LOW signal is output from the gate driver 128), the P-type transistor 142 is turned on, the N-type transistor 143 is turned off, current flows into the blanking interval generating capacitor 140, and the electric potential thereof increases. When the electric potential of the blanking interval generating capacitor 140 then reaches the threshold value voltage of the inverter 141, a LOW signal is output from the inverter 141.
Thus, in the switching power supply apparatus, the oscillation of the switching element is prevented from being halted by a capacitive spike current that is produced when the switching element is turned on, by means of the on-blanking interval generating circuit 131 that generates a blanking pulse signal, which is a LOW signal during the blanking interval and a HIGH signal after the blanking interval has elapsed.
Operation during a load change in the switching power supply device is subsequently described with reference to the timing chart shown in FIG. 9. FIG. 9 is a timing chart of when the load changes from a constant-load condition to a no-load condition or a light-load condition (condition in which the amount of current that flows from the output capacitor 108 to the load 110 is decreasing in comparison with during a constant load).
When the load changes from a constant-load condition to a no-load condition or a light-load condition, in other words, when the load supply current Io (A) decreases, as shown in FIG. 9, the power supply to the load 110 is excessive and the output voltage Vo (B) slightly increases. In response to this, the auxiliary power supply voltage Vcc (C) that is generated by the auxiliary power supply circuit 111 also increases, and the voltage of the error voltage signal VEAO (a) from the error amplifier 122 decreases.
When the voltage of the error voltage signal VEAO (a) decreases, the voltage of the element current detecting signal VCL becomes equivalent to the voltage of the error voltage signal VEAO (a) with a timing that is faster than when at a constant load. As a result, the element current ID (b) flowing through the switching element 105 decreases and the element current detecting signal VCL is also reduced because a control signal for turning off the switching element 105 is output and the ON interval of the switching element 105 is shortened with timing that is faster than when under constant load.
Thus, the switching power supply apparatus adopts a current mode control approach for controlling the current value of the element current ID that flows through the switching element 105, in accordance with the current value of the load supply current Io that is supplied to the load 110.
The element current ID during no load or a light load, and during a heavy load is subsequently described with reference to FIG. 10. FIG. 10 is a diagram that shows the waveform of the element current ID during no load or a light load, and during a heavy load.
During no load or a light load, the energy accumulated in the transformer 104 in the ON interval of the switching element is completely released in the OFF interval. As a result, when the element current ID begins to flow in the subsequent ON interval, the energy in the transformer 104 does not accumulate (non-continuous mode), and the waveform of the element current ID assumes a non-continuous mode waveform (1), as shown in FIG. 10.
During a heavy load, the energy accumulated in the transformer 104 is not completely released in the OFF interval, and when the element current ID begins to flow in the subsequent ON interval, energy remains in the transformer 104 (continuous mode), and the waveform of the element current ID assumes a continuous mode waveform (2), as shown in FIG. 10.
Thus, the generation interval of the capacitive spike current is longer during a heavy load, as shown in FIG. 10, because the element current ID assumes a non-continuous mode waveform (1) during no load or a light load, and a continuous mode waveform (2) during a heavy load. As a result, the blanking interval tBLK must be an interval that is sufficiently long to prevent malfunctioning due to the capacitive spike current even during a heavy load.
Even when the voltage of the element current detecting signal VCL is equal to the voltage of the error voltage signal VEAO and a LOW signal is input to the switching element 105, the element current ID continues to flow until the gate voltage of the switching element 105 reaches a threshold value. The time beginning from when a LOW signal is input to this switching element 105 until the gate voltage of the switching element 105 reaches the threshold value and is turned off is called the element current detecting delay time. With this element current detecting delay time, the element current detecting comparator 124 outputs a HIGH signal because the voltage of the element current detecting signal VCL is greater than the voltage of the error voltage signal VEAO.
The operation from when the switching element is turned on until being turned off is subsequently described with reference to the timing chart in FIG. 11.
The control signal from the gate driver 128 becomes the HIGH signal for turning on the switching element 105, and when the gate voltage (d) of the switching element 105 increases and reaches a threshold value VT, the switching element 105 is turned on and the element current ID (b) begins to flow. A capacitive spike current is produced the instant this element current ID (b) begins to flow.
The on-blanking pulse generating circuit 131 generates a blanking signal (e) that is a LOW signal after the switching element 105 is turned on in the fixed interval (blanking interval tBLK) determined by the capacitance of the blanking interval generating capacitor 140, the threshold value set in the inverter 141, and the current value of the constant current source 144; and is a HIGH signal after the blanking interval tBLK has elapsed.
Thus, even when the comparison signal (f) from the element current detecting comparator is a HIGH signal and the voltage of the error voltage signal (a) is equal to the voltage of the element current detecting signal VCL (c) due to the capacitance spike current, the output signal (g) of the AND circuit 130 remains a LOW signal because the blanking pulse signal (e) from the on-blanking generating circuit 131 is a LOW signal.
After the blanking interval tBLK has elapsed and the blanking pulse signal (e) from the on-blanking generating circuit 131 becomes a HIGH signal, the output signal (g) of the AND circuit 130 becomes a HIGH signal and the gate driver 128 outputs a LOW signal when the voltage of the element current detecting signal VCL (c) is equal to the voltage of the error voltage signal VEAO (a) and the comparison signal (f) from the element detecting comparator is a HIGH signal.
Even when a LOW signal is input to the switching element 105, as described above, the switching element 105 does not turn off until the gate voltage (d) of the switching element 105 reaches the threshold value voltage VT, and the element current ID continues to flow.
In the switching power supply apparatus described above, oscillation of the switching element is prevented from being halted due to a capacitive spike current with the aid of a blanking signal that is generated by the on-blanking pulse generating circuit.
However, in the switching power supply apparatus, the blanking interval is fixed, so there is a possibility that the drawbacks described below may occur.
FIG. 12 is a timing chart that describes the operation that begins when the switching element is turned on during no load or a light load until the system is turned off.
The blanking interval tBLK is set to an interval that is sufficient to allow malfunctioning due to a capacitive spike current to be prevented even during a heavy load, as described above. However, during no load or a light load, a blanking interval tBLK that has been set for times of heavy loads may be too long, and there is possibility that an element current will flow that is equal to or greater than the current value that should flow to the switching element.
In other words, the time from the moment the control signal (HIGH signal) for turning on the switching element is output until the moment the voltage of the error voltage signal VEAO (a) and the voltage of the element current detecting signal VCL (c) become equal to each other is sometimes shorter than the blanking interval tBLK during no load or a light load, as shown in FIG. 12.
In such a case, even when voltages of the error voltage signal VEAO (a) and the element current detecting signal VCL (c) are equal and the comparison signal (f) from the element current detecting comparator 124 is a HIGH signal, the output signal (g) of the AND circuit is a LOW signal and the element current ID (b) continues to flow because the blanking pulse signal (c) from the on-blanking pulse generating circuit is a LOW signal until the blanking interval tBLK has elapsed.
Even when the on-blanking pulse generating circuit outputs a HIGH signal, the element current ID (b) continues to flow during the element current detecting delay time, as described above.
In other words, in a range in which there is no load, a light load, or another condition corresponding to a low current value for the element current ID, the element current value is determined by the minimum pulse interval comprising the blanking internal and the element current detecting delay time, and the value thereof becomes larger than the value that should be controlled by feedback to the output. This results in a drawback whereby more energy than is required is transmitted to the secondary side (output side) of the transformer, and the output voltage Vo becomes equal to or exceeds the prescribed voltage.
When a blanking interval is set in conjunction with times of no load or a light load to resolve the above-stated drawbacks, drawbacks such as those shown in FIG. 13 occur.
In other words, when a blanking interval is set in conjunction with times of no load or a light load, the output signal (g) of the AND circuit 130 becomes a HIGH signal when the voltages of the element current detecting signal VCL (c) and the error voltage signal VEAO (a) become equal to each other due to a capacitive spike current during a heavy load. As a result, a drawback occurs whereby the element current ID (b) flows only for a very short interval, the required energy with respect to the load is not transmitted to the secondary side of the transformer, and the output voltage Vo becomes equal to or less than the prescribed voltage.
As described above, the switching power supply apparatus adopts a current mode control approach in which the element current ID that flows to the switching element during standby or under other conditions of no load or a light load decreases, and, conversely, the element current ID that flows to the switching element during a heavy load increases.
However, with the switching power supply apparatus, the blanking interval tBLK is fixed irrespective of whether the conditions correspond to no load, a light load, or a heavy load.
As a result, when an interval is set that is sufficient to prevent malfunction due to capacitive spike current even during a heavy load, the element current is controlled by the minimum pulse interval during no load or a light load, maximum energy is transmitted to the secondary side, and the output voltage increases excessively.
Conversely, when the blanking interval tBLK is set in accordance with no load or a light load, then a malfunction occurs whereby the switching element is turned off by the capacitive spike current during a heavy load, the interval in which the element current flows is short, the energy required for the load is not transmitted to the secondary side, and the prescribed output voltage cannot be obtained.
In view of the above, a switching power supply apparatus has been proposed in prior art (refer to Japanese Laid-Open Patent Application 2002-112538) that solves the above-stated drawbacks by setting the blanking interval tBLK to an interval that is sufficient to prevent a malfunction due to a capacitive spike current even during a heavy load, and adding dummy resistance. Nevertheless, adding a dummy resistance is disadvantageous in that the power supply efficiency is reduced or the like.